In recent years, a clock and data recovery (CDR) technique has been widely used in data transmission between LSIs. In the CDR technique, various circuit systems have been proposed as disclosed in NPL 1. As a classification affecting the practical use, these circuit systems are classified into a system using a feedback loop for frequency locking and phase locking between a received data signal and a clock signal for a reception circuit, and a system using no feedback loop.
In NPL 1, a PLL-based CDR, a DPLL-based CDR, a combination of PLL/DLL based CDR, a phase interpolator based CDR and an injection locked based CDR have a feedback loop. Among those techniques, the PLL based CDR without reference clock, the digital PLL (DPLL) based CDR, and the combination of PLL/DLL based CDR suffer from a problem that a long time is required for locking in order to feedback both of a frequency and a phase for matching. On the other hand, since both of the frequency and the phase are fed back, there are advantages in that accuracy of the clock signal to be reproduced is high, and a problem on a bit error due to a reduction in the clock precision is less likely to occur.
On the other hand, the PLL-based CDR with an external reference clock, the DLL-based CDR, the phase interpolator (PI) based CDR, and the injection locked based CDR receive a reference clock signal F(ref) from an external, and perform feedback only for phase locking. Therefore, as compared with the CDR feeding back both of the frequency and the phase for matching, there is an advantage in that the time required for locking is short. However, since the clock signal for the reception circuit depends on the reference clock signal F(ref), if there is a shift in frequency between the received data signal and the reference clock signal F(ref), a precision in the clock signal is deteriorated, and bit errors due to the deterioration of precision are likely to occur.
In NPL 1, the gated oscillator based CDR has no feedback loop for both of the frequency and the phase, and the time required for locking is short. However, since the gated oscillator based CDR receives the reference clock signal F(ref) from an external, there arises a problem that the precision in the clock signal is deteriorated due to the frequency error. Also, because an averaging process is not or less performed as the locking time of the phase is shorter, the phase errors are likely to occur.
In NPL 1, the oversampling based CDR is classified into a method using the feedback in the detect bit boundary block, and a method using no feedback. The features of the locking time, the clock precision, and the phase error in both of those systems are also identical with those in the other CDR circuits described above.
Each of the plural circuit systems described above has any advantages and any disadvantages and there is no circuit system excellent in all of those features. In practice, a suitable circuit system is selected depending on the applied use. Therefore, in order to use the same LSI for plural applications, there is a need to produce the plural CDR circuits in the LSI, and appropriately switch one of those CDR circuits to another. However, it is difficult to mount the plural CDR circuits on the LSI in practical application because the chip size increases.